Your complete technical reference for PCB manufacturing, assembly, design, materials, quality inspection, and fabrication specifications. Written by SMTWISE engineers.
Process, materials, stack-ups, DFM rules, copper, HDI, flex, and aerospace standards.
SMT, THT, BGA, solder paste, wave soldering, panelization, and component sourcing.
Layout rules, impedance, high-speed routing, DRC vs DFM, component placement.
Introduction to PCBs, file formats, design software, and basic electronic components.
Via design, blind/buried vias, annular rings, via-in-pad, and through-hole plating.
Scoring, milling, backdrilling, and mechanical fabrication processes.
ENIG, HASL, OSP, immersion silver/tin, hard gold, ENEPIG, and solder mask.
AOI, X-ray, E-test, test coupons, UL certification, and tolerances.
Fabrication specs for rigid, flex, HDI, military grade, and microelectronics PCBs.
The PCB manufacturing process transforms raw substrate material into a precision circuit board through a series of carefully controlled steps. The process begins with substrate preparation — typically FR-4 fiberglass-reinforced epoxy laminate clad with copper foil on one or both sides. The circuit pattern is transferred to the copper through photolithography: a photosensitive resist is applied, exposed through a photomask (generated from your Gerber files), and developed to reveal the copper to be etched away. Chemical etching removes unwanted copper, leaving behind the designed trace pattern.
For multi-layer boards, inner layers are laminated together with prepreg (pre-impregnated fiberglass) under high temperature and pressure in a hydraulic press. Through-holes and vias are then drilled using CNC drilling machines with carbide micro-drill bits at speeds up to 150,000 RPM. The drilled holes are electroplated with copper to create electrical connections between layers. Finally, solder mask is applied for insulation, silkscreen legend is printed for component identification, and the surface finish is applied to protect exposed copper pads.
Aerospace and defense applications demand the highest reliability standards. PCBs for these sectors must comply with IPC-6012DS (Space and Military Avionics Addendum), AS9100 quality management, and often MIL-PRF-31032 for military rigid boards. Key requirements include Class 3/A workmanship per IPC-A-610, IST (Interconnect Stress Testing) coupons on every panel, full lot traceability, ITAR compliance for defense projects, and qualification testing including thermal cycling (-55°C to +125°C), vibration, and humidity exposure.
Copper thieving (also called copper balancing or copper fill) is the practice of adding non-functional copper patterns to areas of the PCB that would otherwise have large voids of bare substrate. This is done to equalize the copper distribution across the board, which prevents uneven plating thickness during the electroplating process. Without copper thieving, areas with sparse copper may receive excessive plating while dense areas are under-plated, leading to impedance variations and reliability issues. Copper thieving patterns are typically dots, crosshatches, or solid fills connected to ground or left floating.
During the lamination process for multi-layer PCBs, the combination of high temperature (170-190°C) and pressure (200-400 PSI) causes the substrate material to shrink. This shrinkage varies by material type, copper distribution, and the number of lamination cycles. To compensate, PCB manufacturers apply scaling factors to the inner layer artwork — slightly enlarging the patterns so that after shrinkage, the features align correctly with the drilled holes. Typical scaling factors range from 0.05% to 0.15% and are calibrated for each material system and stack-up configuration.
IPC-1601A provides comprehensive guidelines for the proper handling, packing, and storage of printed circuit boards to prevent damage from contamination, moisture absorption, mechanical stress, and electrostatic discharge (ESD). Key recommendations include: boards should be stored in moisture-barrier bags with desiccant, shelf life for bare boards with OSP finish is limited to 6 months, boards must be baked before assembly if moisture absorption is suspected, and all handling should use ESD-safe gloves or finger cots to prevent contamination of solderable surfaces.
The PCB stack-up defines the arrangement of copper layers, dielectric materials, and their respective thicknesses. A well-designed stack-up is critical for controlled impedance, signal integrity, power integrity, and EMI compliance. Common configurations include 4-layer (Signal-Ground-Power-Signal), 6-layer (S-G-S-S-P-S), and 8-layer arrangements. Each dielectric layer's thickness and dielectric constant (Dk) directly affects trace impedance, so the stack-up must be designed in conjunction with impedance calculations.
The choice of PCB substrate material depends on the application's electrical, thermal, and mechanical requirements. FR-4 is the industry workhorse — a glass-reinforced epoxy laminate with a Dk of approximately 4.2-4.5 and a glass transition temperature (Tg) of 130-180°C depending on grade. For high-frequency applications above 1GHz, low-loss materials like Rogers RO4003C (Dk=3.38), Isola I-Tera (Dk=3.45), or PTFE-based laminates are essential to minimize signal attenuation. For high-temperature applications, polyimide substrates withstand continuous operation above 250°C.
PTFE (Teflon) laminates offer the lowest dielectric loss (Df < 0.001) and most stable dielectric constant across frequency and temperature, making them ideal for RF and microwave circuits above 10GHz. However, PTFE is expensive, difficult to drill and plate, and requires specialized processing. Non-PTFE alternatives like Rogers RO4000 series provide a good balance of RF performance (Df = 0.0027) with standard FR-4-compatible processing, significantly reducing cost for applications up to 10-12GHz.
Heavy copper PCBs use copper weights of 3oz/ft² (105μm) and above, compared to standard 1oz (35μm). They are used in power electronics, high-current bus bars, and thermal management applications. Heavy copper enables higher current-carrying capacity and better heat dissipation but requires specialized etching processes. Extreme copper boards can go up to 20oz for applications demanding hundreds of amperes.
High Tg (Glass Transition Temperature) PCBs use substrate materials with Tg values above 170°C, compared to standard FR-4 at 130-140°C. High Tg materials maintain mechanical and electrical integrity at elevated temperatures, making them essential for lead-free assembly (which requires higher reflow temperatures of 245-260°C), automotive under-hood applications, and industrial equipment operating in high-temperature environments.
Rogers Corporation manufactures high-performance PCB laminates specifically designed for high-frequency, high-speed, and high-reliability applications. Popular Rogers materials include RO4003C and RO4350B (ceramic-filled hydrocarbon) for cost-effective RF designs, RO3003 (ceramic-filled PTFE) for low-loss microwave circuits, and RT/duroid 5880 (PTFE/glass) for radar and satellite communications. Rogers materials offer tightly controlled dielectric constants (±0.02-0.05) and low loss tangent values.
Flexible PCBs are fabricated on thin, bendable polyimide (Kapton) substrates that can flex thousands of times without failure. They enable 3D circuit routing in space-constrained products like smartphones, cameras, and medical implants. Rigid-flex PCBs combine rigid FR-4 sections (with mounted components) connected by flexible polyimide sections, eliminating connectors and cables while improving reliability. Design considerations include minimum bend radius (typically 6x the total flex thickness), copper type (rolled annealed for dynamic flex, electrodeposited for static applications), and coverlay vs. solder mask for flex protection.
Coverlay is the flexible equivalent of solder mask, used to protect and insulate the copper traces on flexible PCBs. Unlike liquid solder mask which is too brittle for flex applications, coverlay consists of a polyimide film (typically 12.5-25μm) with an adhesive backing that is die-cut to expose pads and laminated onto the flex circuit under heat and pressure. Coverlay provides excellent flexibility, chemical resistance, and electrical insulation, but requires a minimum opening size of 0.2mm and 0.25mm pad-to-coverlay registration tolerance.
High Density Interconnect (HDI) PCBs use microvias (typically 0.1mm diameter laser-drilled), fine traces (3mil or less), and thin dielectrics to achieve dramatically higher routing density than conventional PCBs. HDI technology enables BGA escape routing for 0.4mm-pitch packages, reduces layer count, and improves signal integrity through shorter interconnect lengths. HDI constructions include 1+N+1 (one buildup layer per side), 2+N+2, and any-layer (where every layer is interconnected with stacked or staggered microvias).
Gold fingers (also called edge connectors or card-edge contacts) are gold-plated pads along the edge of a PCB that plug into a mating connector slot. They are used for PCI/PCIe cards, memory modules (DIMMs), and industrial backplane connections. The gold plating (typically hard electrolytic gold at 30-50μin thickness) provides excellent conductivity, corrosion resistance, and wear resistance for hundreds of insertion cycles. Design rules include: beveled board edge (30-45°) for easy insertion, minimum 0.75mm finger width, and nickel underplate (125-200μin) as a barrier layer.
CAM is the process of converting your design data (Gerber files, drill files) into the specific tooling and instructions needed to manufacture your PCB. The CAM engineer reviews your files for manufacturability, generates photo tools, creates drill programs, calculates compensation for etching and plating, and optimizes panel layout for material utilization. A thorough CAM review catches design errors that might otherwise result in defective boards or production delays.
The PCB assembly (PCBA) process transforms a bare printed circuit board into a fully functional electronic assembly by mounting and soldering components. The process varies depending on the component types used — surface mount (SMT), through-hole (THT), or a combination (mixed assembly). A typical SMT assembly flow includes: solder paste printing → solder paste inspection (SPI) → component placement → reflow soldering → automated optical inspection (AOI) → optional X-ray inspection → functional testing. For mixed assemblies, the THT components are inserted after SMT reflow and soldered using wave soldering or selective soldering.
Surface Mount Technology assembly is the predominant method for populating modern PCBs. SMT enables higher component density, smaller board sizes, and faster automated assembly compared to through-hole. Our SMT lines handle components from the smallest 01005 passives (0.4mm × 0.2mm) to large fine-pitch QFP and BGA packages. Key process parameters include solder paste type and mesh size, stencil thickness and aperture design, pick-and-place accuracy, reflow thermal profile, and nitrogen atmosphere for improved wetting on difficult finishes.
NSMD (Non-Solder Mask Defined) pads have the solder mask opening larger than the copper pad, exposing the entire pad for soldering. NSMD pads are preferred for most applications because they provide larger solderable area and better self-centering during reflow. SMD (Solder Mask Defined) pads have the solder mask overlapping the copper pad, defining the solderable area by the mask opening. SMD pads are used when fine-pitch components require precise pad definition or when the copper etch tolerance is looser than the solder mask registration.
An incorrect footprint is one of the most common and costly PCB design errors. Every component footprint must accurately reflect the component's physical dimensions, lead pitch, pad sizes, and courtyard requirements. Best practices include: always design from the manufacturer's recommended land pattern or IPC-7351 guidelines, verify footprint dimensions against the actual component datasheet (not just the symbol), include a 3D model for mechanical clearance verification, and prototype-verify all custom footprints before production.
Clear Pin 1 identification prevents orientation errors during assembly. For ICs, use a dot, triangle, or notch on the silkscreen adjacent to Pin 1. For polarized passives (tantalum capacitors, diodes), mark the cathode band or positive terminal. The assembly house relies on these markings in conjunction with the centroid file to verify component orientation. Additionally, include Pin 1 marking in the solder paste layer for verification during SPI.
Design for Assembly (DFA) rules optimize your PCB layout for efficient, error-free automated assembly. Key DFA rules include: maintain minimum 5mm clearance from board edges for pick-and-place nozzle access, include at least two global fiducials and local fiducials for fine-pitch components, orient all polarized components consistently, provide adequate spacing between tall and short components for nozzle clearance, and design testability access points for ICT or flying probe testing.
Assembly notes are critical instructions included with your assembly drawing that communicate special requirements to the assembly house. Essential assembly notes include: solder alloy specification (SAC305, Sn63/Pb37), IPC workmanship class (Class 2 or Class 3), conformal coating requirements, no-clean vs. water-wash flux, MSL (Moisture Sensitivity Level) bake requirements, and any components requiring manual placement or special handling.
PCB layout is the process of translating a schematic design into a physical circuit board. This involves defining the board outline, placing components in optimal locations, routing signal traces between component pads, designing power distribution networks, and ensuring compliance with manufacturing constraints. A good PCB layout balances electrical performance (signal integrity, power integrity, EMI), thermal management, mechanical constraints, and manufacturability.
Characteristic impedance is the instantaneous ratio of voltage to current in a transmission line. For high-speed digital and RF signals, traces must be designed to a specific impedance (commonly 50Ω single-ended or 100Ω differential) to prevent signal reflections that cause data errors. Impedance is controlled by trace width, trace thickness, dielectric thickness, and dielectric constant (Dk) of the PCB substrate. We provide impedance-controlled stackup design and verify with TDR (Time Domain Reflectometry) measurements on test coupons.
High-speed PCB design requires attention to transmission line effects that become significant when signal rise times are short relative to interconnect propagation delay. Critical rules include: route differential pairs with consistent spacing and matched lengths, avoid routing high-speed signals across split reference planes, minimize via stubs (use backdrilling or HDI blind vias), maintain continuous reference planes under signal traces, control crosstalk by maintaining 3x trace spacing, and use proper termination strategies (series, parallel, AC, or Thevenin) based on the signal topology.
At high frequencies, every PCB feature has parasitic effects that can degrade signal quality. Vias add inductance (typically 0.5-1nH per via) and capacitance. Long traces add resistance and inductance. Component pads add capacitance. Even bypass capacitors have parasitic inductance from their mounting geometry that limits their effective frequency range. Understanding and managing these parasitics through proper component selection, placement, and routing is essential for high-speed design success.
Vias are the vertical interconnects that carry signals and power between PCB layers. Via design impacts signal integrity, power integrity, thermal performance, and manufacturing yield. Standard through-hole vias are drilled mechanically and plated with copper. Microvias (used in HDI designs) are laser-drilled and typically span only one or two layers. Buried vias connect internal layers without extending to the surface. Via parameters include drill size, pad diameter, antipad clearance, and aspect ratio (board thickness to drill diameter).
Component placement is arguably the most impactful phase of PCB layout. Poor placement leads to routing congestion, signal integrity problems, thermal hot spots, and assembly difficulties. Place components in functional groups following the signal flow. Position bypass/decoupling capacitors within 2mm of their associated IC power pins. Keep analog and digital sections separated with a clear boundary. Orient all similar components consistently for automated pick-and-place efficiency. Maintain adequate clearance from board edges, mounting holes, and connectors.
High-frequency PCB design (above 1GHz) demands careful attention to material selection, stackup design, and transmission line geometry. Use low-loss laminates (Rogers, Isola Astra) with tightly controlled Dk values. Minimize the number of signal layer transitions. Use ground-backed coplanar waveguide (GCPW) for impedance control and EMI reduction. Design transitions between different transmission line geometries (microstrip to stripline, coax to PCB) to minimize impedance discontinuities. Simulate critical interconnects with 3D electromagnetic field solvers before fabrication.
For multi-layer PCBs, the orientation of copper layers during fabrication affects registration accuracy and overall board quality. All inner layers should be oriented consistently relative to the panel's grain direction. The outer layers should be positioned symmetrically about the board's center plane to minimize bow and twist. Layer registration is verified using targets placed on each layer during imaging, and typical registration accuracy is ±0.075mm for standard processes and ±0.025mm for HDI.
Thermal vias are arrays of plated through-holes placed beneath heat-generating components (power ICs, LEDs, voltage regulators) to conduct heat from the component pad through the board to a copper plane or heat sink on the opposite side. A properly designed thermal via array can reduce thermal resistance by 50% or more compared to bare substrate. Optimal thermal via design uses via diameter of 0.3mm, pitch of 1.0-1.2mm, and fills the entire thermal pad area. For best performance, vias should be filled and capped to prevent solder wicking during reflow.
Conductive Anodic Filament (CAF) formation is an electrochemical failure mechanism where copper ions migrate along glass fiber-resin interfaces under voltage bias and humidity, creating conductive shorts between conductors. CAF is a significant reliability concern in aerospace and defense applications. Prevention strategies include: using CAF-resistant laminate materials, increasing conductor-to-conductor spacing along glass weave direction, specifying spread-glass or flat-glass fabrics, controlling resin content to minimize fiber-resin delamination, and applying proper moisture management during fabrication and storage.
IPC-2581 is an open, vendor-neutral data transfer standard for PCB design and manufacturing. Unlike the traditional Gerber + drill + BOM approach (which requires multiple separate files), IPC-2581 encapsulates the entire design in a single XML-based file — including layer data, drill information, netlist, BOM, assembly drawings, and fabrication notes. Major EDA tools (Altium, Cadence, Mentor) support IPC-2581 export. Adopting IPC-2581 reduces file management complexity and eliminates data translation errors between design and manufacturing.
IPC defines three classes of electronic products based on reliability requirements. Class 1 (General Electronics) covers consumer products. Class 2 (Dedicated Service Electronics) covers industrial and communications equipment. Class 3 (High Reliability Electronics) covers equipment where failure is not acceptable — medical life support, military, aerospace, and critical infrastructure. Class 3 requires the most stringent workmanship standards including: 100% AOI and X-ray inspection, zero defect acceptance criteria, controlled impedance verification on every lot, microsection analysis of via barrels and copper plating, and full material and process traceability.
HDI design requires different rules and methodologies than conventional PCB design. Key considerations include: use laser-drilled microvias (0.1mm) instead of mechanical drills for layer transitions, plan via stacking or staggering strategy based on reliability requirements, design escape routing from fine-pitch BGAs using dog-bone or via-in-pad patterns, account for sequential lamination registration tolerances when planning layer-to-layer alignment, and work closely with your fabricator to ensure the HDI construction matches their process capabilities.
A Printed Circuit Board (PCB) is a flat board made of insulating material with conductive copper pathways etched onto its surface. These pathways electrically connect electronic components that are soldered onto the board. PCBs are found in virtually every electronic device — from smartphones and laptops to medical equipment and spacecraft. They replaced point-to-point wiring and provided a reliable, reproducible, and scalable method for building electronic circuits.
Several file formats are used to communicate PCB design data between designers and manufacturers. Gerber RS-274X is the most widely used format for layer artwork. Excellon is the standard for drill files. ODB++ is a comprehensive single-file format developed by Valor that includes all manufacturing data. IPC-2581 is the open standard alternative to ODB++. DXF/DWG files are used for mechanical outlines and dimensions. The centroid (pick-and-place) file provides component X/Y coordinates for SMT assembly.
Modern PCB design is performed using specialized Electronic Design Automation (EDA) software. Professional tools include Altium Designer (industry-leading integrated environment), Cadence OrCAD/Allegro (enterprise-level with advanced simulation), Mentor PADS/Xpedition (strong DFM integration), and Zuken CR-8000 (multi-board 3D design). Open-source alternatives include KiCad (rapidly growing, full-featured) and LibrePCB. Each tool has strengths in different areas — schematic capture, constraint-driven routing, signal integrity analysis, or manufacturing output.
Understanding basic electronic components is fundamental to PCB design. Resistors limit current flow and divide voltages. Capacitors store electrical energy and filter noise. Inductors store energy in magnetic fields and filter high-frequency signals. Diodes allow current flow in one direction. Transistors (BJTs, MOSFETs) act as switches or amplifiers. Integrated Circuits (ICs) contain millions of transistors performing complex functions — microcontrollers, memory, power management, and communications. Connectors provide electrical interfaces to external systems.
Vias are the fundamental vertical interconnect structures in multi-layer PCBs. A standard plated through-hole via consists of a drilled hole with electroplated copper connecting all layers it passes through. Key design parameters include drill diameter (minimum 0.2mm for mechanical drilling), pad diameter (drill + 0.15mm minimum annular ring per side), antipad clearance (pad diameter + 0.2mm minimum for inner layer isolation), and aspect ratio (board thickness to drill diameter, typically 8:1 maximum for reliable plating).
Blind vias connect an outer layer to one or more inner layers without passing through the entire board. Buried vias connect internal layers only, with no exposure on either surface. These via types are essential for HDI designs where routing density requires layer transitions without consuming surface real estate. Blind vias are laser-drilled (for microvias spanning 1-2 layers) or mechanically drilled (for deeper structures). Buried vias are drilled and plated on inner layer pairs before lamination into the final stackup.
Via-in-pad technology places vias directly within component pads, typically for BGA escape routing or thermal management. The via must be filled (with conductive or non-conductive epoxy) and planarized (capped with copper) to create a flat, solderable surface. Without filling, solder would wick down into the via during reflow, causing insufficient solder joints. Via-in-pad enables the highest routing density but adds cost due to the filling and planarizing process steps.
The annular ring is the copper pad area surrounding a drilled hole. It ensures reliable electrical connection between the via barrel plating and the trace or plane connected to that via. Minimum annular ring requirements depend on the IPC class: Class 2 allows 0.05mm minimum, while Class 3 requires 0.05mm minimum with zero breakout tolerance. Annular ring violations are one of the most common DFM issues, particularly when drill registration tolerance consumes the designed annular ring.
Via tenting covers the via openings with solder mask to prevent solder from entering the via during assembly. Tenting is suitable for vias with drill diameters up to 0.3mm; larger vias may cause the solder mask film to crack or dimple. Alternatives include via plugging (filling with epoxy or solder mask), via capping (metal cap over a filled via), and leaving vias open (for non-critical vias away from component pads). The choice depends on via size, proximity to components, and reliability requirements.
Castellated holes (plated half-holes) are plated through-holes positioned at the board edge and then routed through their center, creating half-cylindrical plated features along the board edge. They are used to create solderable module-to-PCB connections for wireless modules, sensor boards, and other daughter-card applications. Design requires: minimum 0.6mm hole diameter, the holes must be registered precisely to the board outline, and copper plating must extend continuously around the half-barrel for reliable solder wetting.
An antipad is the clearance hole in a copper plane (ground or power) that provides electrical isolation around a via or through-hole that should not be connected to that plane. The antipad diameter must be large enough to prevent shorting between the via barrel and the plane copper, accounting for drill registration tolerance and etching variation. Typical antipad clearance is 0.2-0.25mm per side beyond the via pad diameter. For impedance-controlled vias, antipad size directly affects the via's parasitic capacitance.
CNC drilling is performed using tungsten carbide micro-drill bits at speeds of 80,000-150,000 RPM. Entry and exit materials (aluminum and phenolic backing) are used to reduce burring. After drilling, the holes are cleaned (desmeared) to remove resin smear from the drill heat, then chemically activated and electroplated with copper (typically 20-25μm minimum barrel plating per IPC Class 2). The plating process must produce uniform, void-free copper throughout the via barrel for reliable electrical and thermal conductivity.
Countersink holes are conical recesses that allow flat-head screws to sit flush with the board surface. Counterbore holes are cylindrical recesses for socket-head cap screws or press-fit connectors. Both are created as secondary mechanical operations after PCB fabrication. Design specifications must include hole diameter, recess diameter, recess depth, and tolerance for each feature. These holes are non-plated and must maintain adequate clearance from copper features and board edges.
Side plating (also called edge plating or castellated edge plating) deposits copper along the edges of a PCB to create a continuous ground connection around the board perimeter or to enable soldering to the board edge. This technique is commonly used for EMI shielding (creating a Faraday cage when combined with ground planes) and for module interconnection. The plating wraps from the top surface around the routed edge to the bottom surface, providing a continuous conductive path.
Surface finish protects exposed copper pads from oxidation and provides a solderable surface for component assembly. The choice of surface finish affects solderability, shelf life, planarity (for fine-pitch components), cost, and environmental compliance.
HASL is the most traditional and cost-effective surface finish. The board is dipped in molten solder and excess is removed by hot air knives. HASL provides excellent solderability and long shelf life (12+ months) but produces uneven pad surfaces that are unsuitable for fine-pitch components (< 0.5mm pitch). Available in leaded (Sn63/Pb37) and lead-free (SAC305) versions.
ENIG deposits a layer of electroless nickel (3-6μm) followed by a thin immersion gold layer (0.05-0.125μm). The gold protects the nickel from oxidation during storage, and the nickel provides a flat, solderable barrier between the copper and the gold. ENIG offers excellent planarity for fine-pitch components, good shelf life (12 months), and is suitable for wire bonding. The primary concern is "black pad" — a defect caused by excessive phosphorus in the nickel that can cause brittle solder joints.
OSP applies a thin organic compound (typically benzotriazole or imidazole) that selectively bonds to copper, protecting it from oxidation. OSP is the most environmentally friendly and lowest-cost finish. It provides excellent planarity for fine-pitch assembly. However, OSP has a shorter shelf life (6 months), is not suitable for multiple reflow cycles (the coating degrades with each thermal exposure), and is invisible — making visual inspection of coverage difficult.
Immersion silver deposits a thin layer (0.15-0.4μm) of silver directly on copper through a displacement reaction. It provides excellent solderability, good planarity, and compatibility with all solder alloys. Silver finish has moderate shelf life (6-12 months when properly stored) and must be protected from sulfur-containing environments that cause tarnishing. Immersion silver is popular for high-frequency applications because silver has the highest electrical conductivity of any metal.
Immersion tin deposits a thin layer of tin (0.8-1.2μm) on copper through chemical displacement. It provides good solderability and flat surface for fine-pitch components. However, tin finish is prone to tin whisker growth (a reliability concern for aerospace and military applications) and has a limited shelf life (3-6 months). It requires careful handling to prevent finger oils and scratches from degrading the surface.
Hard gold is electroplated gold alloyed with cobalt or nickel (99.7% Au, 0.3% Co/Ni) to a thickness of 0.75-1.25μm over a nickel barrier layer. It provides exceptional wear resistance (suitable for hundreds of mating cycles), corrosion resistance, and contact reliability. Hard gold is used for edge connectors (gold fingers), test points, and switch contacts. It is significantly more expensive than other finishes and is typically applied selectively to contact areas only.
ENEPIG adds a palladium layer (0.05-0.15μm) between the nickel and gold layers of ENIG. The palladium acts as an additional barrier that prevents the "black pad" nickel corrosion issue while enabling both solder assembly and wire bonding on the same board. ENEPIG is considered a universal finish suitable for all assembly methods — SMT, THT, wire bonding (gold and aluminum wire), and press-fit connectors — making it increasingly popular despite its higher cost.
EPIG eliminates the nickel layer entirely, depositing palladium (0.2-0.5μm) directly on copper followed by immersion gold. This eliminates any risk of black pad and provides excellent wire bondability. EPIG is primarily used in semiconductor packaging and advanced electronic assemblies where the nickel layer's magnetic properties or potential corrosion are concerns.
Solder mask is the colored coating (typically green, but available in blue, red, black, white, and yellow) applied over the copper traces of a PCB. It serves multiple functions: preventing solder bridges between closely spaced pads during assembly, protecting copper traces from oxidation and contamination, providing electrical insulation between conductors, and improving the board's appearance. Liquid Photo-Imageable (LPI) solder mask is the industry standard, applied by screen printing or curtain coating and UV-exposed through a photo tool to define pad openings.
The silkscreen (legend) layer contains printed text, component outlines, reference designators, logos, and other markings that aid in assembly, testing, and servicing. Silkscreen is typically white ink on green solder mask, but any color combination is available. Key design rules: minimum line width of 0.15mm (6mil), minimum character height of 1mm, silkscreen must not overlap exposed copper pads (it interferes with soldering), and text should be oriented consistently for readability.
AOI systems use high-resolution cameras and advanced image processing algorithms to inspect every PCB for defects at production speed. 3D AOI systems add height measurement capability to detect lifted leads, tombstoned components, and insufficient solder volume. Our AOI systems inspect for: missing components, wrong components, misaligned components, wrong polarity, solder bridges, insufficient solder, excess solder, tombstoning, and damaged components. AOI is performed after reflow soldering and provides 100% inspection coverage that is impossible with manual visual inspection.
X-ray inspection is essential for verifying solder joints hidden beneath BGA, QFN, LGA, and bottom-terminated component packages. Our high-resolution 2D and CT (computed tomography) X-ray system can detect: solder voiding (void percentage and distribution), head-in-pillow defects (partial ball collapse), cold solder joints, solder bridging between adjacent balls, missing solder balls, and barrel fill percentage for through-hole joints. IPC-A-610 specifies maximum acceptable void area of 25% for BGA solder joints.
Electrical testing verifies the connectivity and isolation of every circuit on a bare PCB before assembly. Two methods are common: flying probe testing (two or four motorized test probes that move to each test point sequentially — ideal for prototypes and small volumes) and bed-of-nails testing (a custom fixture with spring-loaded pins contacting all test points simultaneously — ideal for high-volume production). E-test detects open circuits, short circuits, and can measure impedance on controlled-impedance designs.
Test coupons are standardized patterns fabricated on the manufacturing panel alongside your production boards. They serve as sacrificial samples for destructive quality verification without consuming production boards. Common coupon types include: plating thickness coupons (cross-sectioned to measure copper thickness in via barrels), impedance test coupons (TDR-measured to verify controlled impedance values), thermal stress coupons (solder float tested at 288°C for 10 seconds to verify plating integrity), and IST coupons (Interconnect Stress Test for thermal cycling reliability).
Understanding manufacturing tolerances is essential for designing PCBs that are both high-performance and reliably manufacturable. Critical tolerances include: trace width (±0.025mm), trace spacing (±0.025mm), drill size (±0.05mm), hole position (±0.075mm), registration layer-to-layer (±0.075mm standard, ±0.025mm HDI), board thickness (±10%), impedance (±10% standard, ±5% tight control), solder mask registration (±0.05mm), and silkscreen registration (±0.1mm).
UL (Underwriters Laboratories) certification ensures that PCBs meet safety requirements for the intended application. UL recognition requires the PCB manufacturer to undergo facility audits, demonstrate process control, and test boards for flammability (UL 94 rating), electrical strength, and thermal resistance. UL-certified boards carry a UL marking and file number traceable to the manufacturer's recognition. Most commercial and consumer products require UL-recognized PCBs for market access in North America.
V-scoring creates a V-shaped groove along the separation line between PCBs in a panel, allowing boards to be snapped apart after assembly. The groove is cut from both sides of the panel, typically removing one-third of the board thickness from each side, leaving one-third as a web. V-scoring produces a straight edge but generates stress that can damage nearby components — maintain minimum 1mm clearance between the score line and the nearest component or trace.
Jump scoring is a variation of V-scoring where the scoring blade lifts at specific locations along the score line, creating reinforced sections (tabs) that hold the panel together more securely during assembly. This technique is useful when boards require additional panel rigidity for SMT processing or when certain areas need protection from scoring-induced stress. After assembly, boards are separated by manually breaking the remaining tabs.
Tab-route milling uses CNC routing to cut the board outline, leaving small breakaway tabs that hold individual boards within the panel. After assembly, boards are depaneled by breaking or cutting the tabs. Milling provides more design flexibility than V-scoring (supporting irregular board outlines) and doesn't create stress on nearby components. Tab design should include mouse-bite perforations (a line of small drilled holes) for clean, controlled separation.
Beyond drilling and routing, several mechanical processes are used in PCB fabrication: scoring (V-groove for depaneling), beveling (angling board edges for card-edge connectors), countersinking (recessed holes for flush-mount screws), depth routing (milling to a controlled depth without penetrating the board), back-routing (removing copper from specific areas on a completed board), and edge plating (depositing copper on routed board edges for grounding or shielding).
Backdrilling removes the unused portion (stub) of a plated through-hole via that extends beyond its intended connection layers. Via stubs act as resonant antennas that cause signal reflections and impedance discontinuities at frequencies above 3-5GHz. Backdrilling is performed by re-drilling the via from the back side with a slightly larger drill bit to a controlled depth, removing the stub copper while preserving the functional via barrel. This technique is widely used in high-speed networking, server, and telecommunications equipment operating at data rates above 10Gbps.
Comprehensive fabrication notes ensure your board is manufactured exactly as intended. Essential notes include: material specification (FR-4, Rogers, etc.), copper weight per layer, board thickness and tolerance, surface finish type and thickness, solder mask color and type (LPI), silkscreen color, impedance requirements with target values and tolerance, IPC class designation, UL flammability rating, special requirements (filled vias, blind/buried vias, controlled depth drilling), and panel/array specifications.
Standard rigid PCB capabilities: Layer count: 1-40 layers. Material: FR-4, high-Tg FR-4, halogen-free, polyimide, Rogers. Board thickness: 0.2mm - 6.0mm. Copper weight: 0.5oz - 10oz (standard), up to 20oz (heavy copper). Minimum trace/space: 3/3mil (standard), 2/2mil (advanced). Minimum drill: 0.15mm (mechanical), 0.075mm (laser). Surface finish: HASL, ENIG, OSP, immersion silver/tin, ENEPIG, hard gold. Impedance control: ±10% standard, ±5% tight tolerance.
Flexible PCB capabilities: Layer count: 1-8 layers. Material: polyimide (Kapton). Total thickness: 0.05mm - 0.5mm. Copper type: rolled annealed (RA) for dynamic flex, electrodeposited (ED) for static applications. Coverlay material: polyimide film with acrylic or epoxy adhesive. Minimum bend radius: 6x total flex thickness (dynamic), 3x (static). Stiffener options: FR-4, polyimide, stainless steel, aluminum.
HDI capabilities: Microvia diameter: 0.075-0.15mm (laser drilled). Buildup layers: 1+N+1, 2+N+2, 3+N+3, any-layer. Minimum trace/space: 2/2mil. Microvia aspect ratio: 0.8:1 maximum. Stacked microvias: up to 3 levels (with copper-filled vias). Sequential lamination cycles: up to 4. Materials: standard FR-4, high-Tg, low-loss. Applications: smartphones, SSD controllers, FPGA carrier boards, medical implants.
Military grade PCB requirements (per MIL-PRF-31032 and IPC-6012DS): Workmanship: IPC Class 3/A. Material: MIL-qualified laminates with full lot traceability. Testing: IST (Interconnect Stress Test) and thermal shock (100 cycles, -65°C to +125°C). Plating: minimum 25μm barrel copper, minimum 2.5μm nickel, minimum 1.27μm gold for edge connectors. Cleanliness: ionic contamination < 1.56μg NaCl/cm². Documentation: full material certificates, process travelers, and inspection data packages (IDPs). ITAR compliance required for classified programs.
Our Turnkey PRO service includes advanced capabilities: DFM/DFA review within 4 hours, component sourcing from authorized distributors only, humidity-controlled storage for MSL components, nitrogen-atmosphere reflow, 3D AOI + X-ray inspection, ICT or flying probe test development, conformal coating (acrylic, silicone, or urethane), potting and encapsulation, cable and harness assembly, final box-build integration, and full documentation package (test reports, certificates of conformance, first article inspection reports).
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